The present invention relates generally to circuit power management schemes, and more particularly, to methods, systems and apparatus for managing power consumption in memory circuits.
Prior art circuit power management schemes for flash memory circuits model a power consumption of each flash task that the flash memory circuit may be expected to execute. The power consumption model of each flash task is defined by a worst-case value observed in worst case environmental context (e.g., temperature, data pattern, user scenario, circuit component aging, etc.) of each of those tasks on a selected number of samples.
As each flash task appears in the pipeline, the flash tasks are delayed or executed based upon the worst-case scenario modeled power consumption such that an average power cap in a sliding execution window (e.g., a 16 millisecond sliding execution window) is not exceeded. All currently running tasks are summed to evaluate an average consumption, typically, the actual power consumption values are significantly lower than worst case power consumption values that are used for average calculation.
The prior art power consumption model of each flash task is static, meaning that once the model is defined, sometime during the manufacturing process, the model remains the same throughout the life of the memory device. Unfortunately many different dynamic execution conditions can occur that can change the actual power consumption of a given task. By way of example, an operating temperature, an age, a task execution order, a task execution rate demand, etc., can cause the actual power consumption being greater or lower than the static model that was created when the device was manufactured.
As a result, the prior art power consumption model of each flash task always forces the performance of each flash task to be artificially degraded to account for worst-case scenario, even when the worst-case scenario does not occur. Thus the performance of the memory device is often degraded excessively and unnecessarily. Further, the static, prior art power consumption model that was created when the device is manufactured cannot and does not account for possible dynamic changes and thus may not even limit the power consumption to less than the power cap. Further still, the static, prior art power consumption model is an open loop type system because there is no feedback.
In view of the foregoing, there is a need for a dynamic power consumption model of each task that accurately and dynamically reflects the actual execution conditions so as to more efficiently operate the memory circuit.